Digital Design (CS207)
Introduction to digital circuit design and analysis, along with programming in Verilog to describe the circuit for simulation and running on FPGA.
About
- Instructor:
Yuhui BAI (白雨卉) - TA:
Wei WANG (王薇) - Semester:
2023 Fall - Textbook:
Digital Design with an Introduction to the Verilog HDL
Content
| Chapter | Content | Note |
|---|---|---|
| Number System | Radix Conversion Complement of number Code: BCD, Gray, Error Detection Signed Binary |
\(r\)'s Complement \(r-1\)'s Complement |
| Boolean Algebra | Properties of AND and OR Truth Table Simplification Canonical and Standard form |
SOP POS Minterm Maxterm |
| Gate Level Minimization | K-map Don't care condition |
Simplification Method |
| Two Level Implementation | AND-OR = NAND-NAND = SOP OR-AND = NOR-NOR = POS NAND-AND = AND-NOR = AOI OR-NAND = NOR-OR = OAI |
The last two are generated from the invert of the first two |
| Combinational Logic | Design and Analysis of Circuit | Truth Table -- K Map -- Simplified Equation -- Diagram |
| Standard Components | Decoder Multiplexer Encoder |
Implementation and Usage of them |
| Latches and Flip-Flops | SR / D Latch SR / D / JK / T Flip-Flops |
Input equation and function tables |
| Sequential Logic | Design and Analysis of Finite State Machine (Moore & Mealy) | State Diagram -- State Table -- State Equation and Output Equation -- Choose FF and Input Equation -- Diagram |
| Registers and Counters | Serial and Parallele Register Synchronous and Aschronous Counter |
Function Table and Sequence Generator |
| Arithmetic Circuit | Binary Adder-Subtractor Decimal Adder Multiplier |
Combination of the Components |