Computer Organization (CS202)
About
- Instructor:
Yuhui BAI (白雨卉) - TA:
Qing WANG (王晴) - Semester:
2024 Spring - Textbook:
Computer Organization and Design: The Hardware/Software Interface
Content
| Lecture | Topic | Note |
|---|---|---|
| lec1 | Syllabus and Overview | Intro to the principles of computer processor |
| lec2 | ISA, RISC-V and Intro to Assembly | RISC-V is an ISA (Instruction Set Architecture) Programming in RISC-V Assembly Code |
| lec3 | Control Flow and Stack | Direct and Conditional Branch Calling Convention in RISC-V |
| lec4 | Binary Format | Structure of RISC-V Machine Code |
| lec5 | Performance Measurement | Calculation of Processor's Performance: CPI and SPEC |
| lec6 | Execution of Integers | Add, Substraction, Multiplication and Division |
| lec7 | Float Point Number (Decimal) Arithmetic | Standard for Float and Double Add/Sub, Mul/Div of FP Matrix Operation, SIMD |
| lec8 | Single-Cycle Processor Design | Elements in CPU Data Path Clocking Methodology |
| lec9 | Pipelined CPU Design | Stage Register Hazards and Solution |
| lec10 | Instruction-Level Parallelism | Statical Multi-issue Design Loop Unrolling Hazards |
| lec11 | Intro to Cache | Functions and Strategies of Direc-Mapped Cache |
| lec12 | Cache Cont'd | N-way Set Associative Cache Full Associative Cache Efficiency Measurement Multi-Level Cache |
| lec13 | Virtual Memory | Page Table Address Translation Replacement & TLB |
| lec14 | Multi-Core Concepts | Calculation of Multi-Core Speedup Multithreading Intro to GPU |
Summary: Processor, Memory, Parallel. Design and Data Path, every detail matters.
Project
The project topic remains the (possibly) forever, to build a CPU from scratch. Though the codes are available online, it's strongly recommended to write your own without referring to any existing code. General steps are as follows: 1. Understanding the design of single-cycle CPU from the textbook but I won't suggest referring it due to the flaws in that design. 2. Based on your understanding, draw the figure of your CPU from scratch, which means to redesign the datapath within your mind without referring the textbook, on paper or using any software like draw.io. 3. Pay attention to the scalability of your design, i.e., how to extend the ISA esaily in your design. And you will know why textbook is wrong. 4. Try implemeting the full version of RV32I, or it'll be hard to extend the ISA in the future since it requires to modify the design heavily. 5. On the basis of well-functioning, try to optimize the design, like pipelining, hazard handling, cache, branch prediction, etc.
Have fun with your CPU design!